Field
The present disclosure relates generally to electronic circuits, and more particularly, to pulse latch for use with memory and other devices.
Background
An integrated circuit (IC) may have more than one group of components, where each group of components is designed to operate at a different voltage level. For example, a first group of components may be designed to operate at a first voltage level, and a second group of components may be designed to operate at a second, different voltage level. Integrated circuits that are designed with groups of components operating at more than one voltage level are said to have multiple power domains, where each power domain is associated with a particular voltage level. In operation, a particular power domain may be selectively powered up or down by controlling power to the network of circuit wirings connecting the group of components in that power domain.
Because memory circuits and chip logic circuits have different voltage requirements, memory circuits and chip logic circuits usually reside in different power domains. For example, memory circuits may reside in a power domain called memory domain and chip logic circuits may reside in a power domain called chip domain. There may be a large difference between the voltage level of the memory domain and the voltage level of the chip domain.
A memory device is commonly used in many electronics devices, such as computers, wireless communication devices, personal digital assistants (PDAs), and other electronic devices. A memory device typically includes a large number of memory cells for storing data. A read circuit may be used to read data from the memory cells and a write circuit may be used to write data to the memory cells. The read circuit may include a pulse latch circuit for generating a read clock. Similarly, the write circuit may include a pulse latch circuit for generating a write clock. The read and write clocks are used to access the memory cells. The ability to properly access these memory cells often depends on the stability of the pulse latches used to generate the read and write clocks.